BEL Requirement OF DEPUTY ENGINEER Last Date 01/04/15

This is a company which deals with a wide spectrum of products ranging from Radars to Solar based solutions. BEL goes much beyond the defence products they are famous for, they have made inroads into civilian products as well.

1 DEPUTY ENGINEER (D&E) – FRONT END DESIGN & VERIFICATION ENGINEER

 No. of posts: 01

 Qualification: M.Tech in Micro Electronics/Electronic from any AICTE approved

institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates.

 Experience: 2 years post qualification experience in working with ARM processor IP and

other IPs (PCIe, Ethernet, CAN, USB, GPU etc.), HDLs (Verilog, VHDL) with

VERA/System C/System Verilog, IP validation, HVL methodology (UVM, OVM),

2 DEPUTY ENGINEER (D&E) – ASIC IMPLEMENTATION ENGINEER

 No. of posts: 01

 Qualification: M.Tech in Micro Electronics/Electronic System from any AICTE

approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates.

 Experience: 2 years of post qualification experience in Design synthesis of RTL designs

and block/chip level timing constraints, formal verification at RTL and netlist level,

timing closure methodologies, for 65nm and below with complexity of more than 10

3. DEPUTY ENGINEER (D&E) – PHYSICAL DESIGN ENGINEER

 No. of posts: 02

 Qualification: M.Tech in Micro Electronics/Electronic System from any AICTE

approved institution with First class for GEN/OBC and Pass for SC/ST/PWD candidates.

 Experience: 2 years of post qualification experience in place and route methodologies

(floor planning, placement, CTS, P&R, power routing) with timing convergence and

solving PNR issues, using hard marco IPs, standard cell P&R, foundry and third party I/Os,

tapeouts for 65nm and below process node with complexity of at least 10 million gates,

usage of state of the art automated P&R tools of MG/Cadence/Magma/Synopsistools for

physical design and verification, RC extraction, parasitic extraction, IR drop analysis,

thermal analysis/antenna checks/optical correction, LVS/DRC/ERC and other physical

verification checks for 65nm and below, signoff task methodologies, including timing

closure with crosstalk and On Chip Variation (OCV) under multimode multicomer

condition, scripting (perl, TCL).

Application Fee - ₹500

Sr.Deputy General Manager (HR) / Components & EM, Bharat Electronics Limited,

Jalahalli Post, Bangalore – 560 013 on or before 01.04.2015.

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